pyslang Verilog/SystemVerilog Analysis

MCP server providing 10 compiler-backed read-only analysis tools for Verilog and SystemVerilog projects.

Delivers compiler-backed analysis for Verilog and SystemVerilog hardware description language projects using pyslang. Provides tools for parsing HDL files, diagnostics, hierarchy inspection, and symbol lookup with project-root scoping for safe read-only access. Distributed as the `pyslang-mcp` package on PyPI.