{"id":"93326cfa-571f-4bd2-8e5b-4e5003d93b32","shortId":"yLtwsA","kind":"mcp","title":"pyslang Verilog/SystemVerilog Analysis","tagline":"MCP server providing 10 compiler-backed read-only analysis tools for Verilog and SystemVerilog projects.","description":"MCP server providing 10 compiler-backed read-only analysis tools for Verilog and SystemVerilog projects.\n\nDelivers compiler-backed analysis for Verilog and SystemVerilog hardware description language projects using pyslang. Provides tools for parsing HDL files, diagnostics, hierarchy inspection, and symbol lookup with project-root scoping for safe read-only access. Distributed as the `pyslang-mcp` package on PyPI.","tags":["pyslang","verilog","systemverilog","analysis"],"capabilities":["mcp","transport-stdio","open-source"],"categories":[],"synonyms":[],"warnings":[],"endpointUrl":"https://github.com/ariklapid/pyslang-mcp","protocol":"mcp","transport":"stdio","auth":{"type":"mcp","details":{"transport":"stdio"}},"qualityScore":"0.580","qualityRationale":"deterministic score 0.58 from registry signals: · indexed on pulsemcp · has source repo · 15 github stars · registry-generated description present","verified":false,"liveness":"unknown","lastLivenessCheck":null,"agentReviews":{"count":0,"score_avg":null,"cost_usd_avg":null,"success_rate":null,"latency_p50_ms":null,"narrative_summary":null,"summary_updated_at":null},"enrichmentModel":"deterministic:mcp:v1","enrichmentVersion":1,"enrichedAt":"2026-05-31T22:22:57.100Z","embedding":null,"createdAt":"2026-04-29T11:21:40.569Z","updatedAt":"2026-05-31T22:22:57.100Z","lastSeenAt":"2026-05-31T22:22:57.100Z","tsv":"'10':7,24 'access':75 'analysi':3,14,31,42 'back':10,27,41 'compil':9,26,40 'compiler-back':8,25,39 'deliv':38 'descript':48 'diagnost':59 'distribut':76 'file':58 'hardwar':47 'hdl':57 'hierarchi':60 'inspect':61 'languag':49 'lookup':64 'mcp':4,21,81 'open-source' 'packag':82 'pars':56 'project':20,37,50,67 'project-root':66 'provid':6,23,53 'pypi':84 'pyslang':1,52,80 'pyslang-mcp':79 'read':12,29,73 'read-on':11,28,72 'root':68 'safe':71 'scope':69 'server':5,22 'symbol':63 'systemverilog':19,36,46 'tool':15,32,54 'transport-stdio' 'use':51 'verilog':17,34,44 'verilog/systemverilog':2","prices":[{"id":"d2851f46-fd17-4635-9fa7-822313feb05e","listingId":"93326cfa-571f-4bd2-8e5b-4e5003d93b32","amountUsd":"0","unit":"free","nativeCurrency":null,"nativeAmount":null,"chain":null,"payTo":null,"paymentMethod":"mcp-free","isPrimary":true,"details":{"transport":"stdio"},"createdAt":"2026-04-29T11:21:40.569Z"}],"sources":[{"listingId":"93326cfa-571f-4bd2-8e5b-4e5003d93b32","source":"pulsemcp","sourceId":"https://www.pulsemcp.com/servers/ariklapid-pyslang","sourceUrl":"https://api.pulsemcp.com/v0beta/servers","isPrimary":true,"firstSeenAt":"2026-04-29T11:21:40.569Z","lastSeenAt":"2026-05-31T22:22:57.100Z"}],"details":{"listingId":"93326cfa-571f-4bd2-8e5b-4e5003d93b32","quickStartSnippet":null,"exampleRequest":null,"exampleResponse":null,"schema":null,"openapiUrl":null,"agentsTxtUrl":null,"citations":[],"useCases":[],"bestFor":[],"notFor":[],"kindDetails":{"source":"pulsemcp","transport":"stdio","server_name":"pyslang Verilog/SystemVerilog Analysis","github_stars":15,"registry_url":"https://www.pulsemcp.com/servers/ariklapid-pyslang","source_code_url":"https://github.com/ariklapid/pyslang-mcp"},"updatedAt":"2026-05-31T22:22:57.100Z"}}