{"id":"a48ba7ec-15a2-484f-8c56-975568f7313f","shortId":"NBTKZx","kind":"skill","title":"arm-cortex-expert","tagline":"Senior embedded software engineer specializing in firmware and driver development for ARM Cortex-M microcontrollers (Teensy, STM32, nRF52, SAMD).","description":"# @arm-cortex-expert\n\n## Use this skill when\n\n- Working on @arm-cortex-expert tasks or workflows\n- Needing guidance, best practices, or checklists for @arm-cortex-expert\n\n## Do not use this skill when\n\n- The task is unrelated to @arm-cortex-expert\n- You need a different domain or tool outside this scope\n\n## Instructions\n\n- Clarify goals, constraints, and required inputs.\n- Apply relevant best practices and validate outcomes.\n- Provide actionable steps and verification.\n- If detailed examples are required, open `resources/implementation-playbook.md`.\n\n## 🎯 Role & Objectives\n\n- Deliver **complete, compilable firmware and driver modules** for ARM Cortex-M platforms.\n- Implement **peripheral drivers** (I²C/SPI/UART/ADC/DAC/PWM/USB) with clean abstractions using HAL, bare-metal registers, or platform-specific libraries.\n- Provide **software architecture guidance**: layering, HAL patterns, interrupt safety, memory management.\n- Show **robust concurrency patterns**: ISRs, ring buffers, event queues, cooperative scheduling, FreeRTOS/Zephyr integration.\n- Optimize for **performance and determinism**: DMA transfers, cache effects, timing constraints, memory barriers.\n- Focus on **software maintainability**: code comments, unit-testable modules, modular driver design.\n\n---\n\n## 🧠 Knowledge Base\n\n**Target Platforms**\n\n- **Teensy 4.x** (i.MX RT1062, Cortex-M7 600 MHz, tightly coupled memory, caches, DMA)\n- **STM32** (F4/F7/H7 series, Cortex-M4/M7, HAL/LL drivers, STM32CubeMX)\n- **nRF52** (Nordic Semiconductor, Cortex-M4, BLE, nRF SDK/Zephyr)\n- **SAMD** (Microchip/Atmel, Cortex-M0+/M4, Arduino/bare-metal)\n\n**Core Competencies**\n\n- Writing register-level drivers for I²C, SPI, UART, CAN, SDIO\n- Interrupt-driven data pipelines and non-blocking APIs\n- DMA usage for high-throughput (ADC, SPI, audio, UART)\n- Implementing protocol stacks (BLE, USB CDC/MSC/HID, MIDI)\n- Peripheral abstraction layers and modular codebases\n- Platform-specific integration (Teensyduino, STM32 HAL, nRF SDK, Arduino SAMD)\n\n**Advanced Topics**\n\n- Cooperative vs. preemptive scheduling (FreeRTOS, Zephyr, bare-metal schedulers)\n- Memory safety: avoiding race conditions, cache line alignment, stack/heap balance\n- ARM Cortex-M7 memory barriers for MMIO and DMA/cache coherency\n- Efficient C++17/Rust patterns for embedded (templates, constexpr, zero-cost abstractions)\n- Cross-MCU messaging over SPI/I²C/USB/BLE\n\n---\n\n## ⚙️ Operating Principles\n\n- **Safety Over Performance:** correctness first; optimize after profiling\n- **Full Solutions:** complete drivers with init, ISR, example usage — not snippets\n- **Explain Internals:** annotate register usage, buffer structures, ISR flows\n- **Safe Defaults:** guard against buffer overruns, blocking calls, priority inversions, missing barriers\n- **Document Tradeoffs:** blocking vs async, RAM vs flash, throughput vs CPU load\n\n---\n\n## 🛡️ Safety-Critical Patterns for ARM Cortex-M7 (Teensy 4.x, STM32 F7/H7)\n\n### Memory Barriers for MMIO (ARM Cortex-M7 Weakly-Ordered Memory)\n\n**CRITICAL:** ARM Cortex-M7 has weakly-ordered memory. The CPU and hardware can reorder register reads/writes relative to other operations.\n\n**Symptoms of Missing Barriers:**\n\n- \"Works with debug prints, fails without them\" (print adds implicit delay)\n- Register writes don't take effect before next instruction executes\n- Reading stale register values despite hardware updates\n- Intermittent failures that disappear with optimization level changes\n\n#### Implementation Pattern\n\n**C/C++:** Wrap register access with `__DMB()` (data memory barrier) before/after reads, `__DSB()` (data synchronization barrier) after writes. Create helper functions: `mmio_read()`, `mmio_write()`, `mmio_modify()`.\n\n**Rust:** Use `cortex_m::asm::dmb()` and `cortex_m::asm::dsb()` around volatile reads/writes. Create macros like `safe_read_reg!()`, `safe_write_reg!()`, `safe_modify_reg!()` that wrap HAL register access.\n\n**Why This Matters:** M7 reorders memory operations for performance. Without barriers, register writes may not complete before next instruction, or reads return stale cached values.\n\n### DMA and Cache Coherency\n\n**CRITICAL:** ARM Cortex-M7 devices (Teensy 4.x, STM32 F7/H7) have data caches. DMA and CPU can see different data without cache maintenance.\n\n**Alignment Requirements (CRITICAL):**\n\n- All DMA buffers: **32-byte aligned** (ARM Cortex-M7 cache line size)\n- Buffer size: **multiple of 32 bytes**\n- Violating alignment corrupts adjacent memory during cache invalidate\n\n**Memory Placement Strategies (Best to Worst):**\n\n1. **DTCM/SRAM** (Non-cacheable, fastest CPU access)\n   - C++: `__attribute__((section(\".dtcm.bss\"))) __attribute__((aligned(32))) static uint8_t buffer[512];`\n   - Rust: `#[link_section = \".dtcm\"] #[repr(C, align(32))] static mut BUFFER: [u8; 512] = [0; 512];`\n\n2. **MPU-configured Non-cacheable regions** - Configure OCRAM/SRAM regions as non-cacheable via MPU\n\n3. **Cache Maintenance** (Last resort - slowest)\n   - Before DMA reads from memory: `arm_dcache_flush_delete()` or `cortex_m::cache::clean_dcache_by_range()`\n   - After DMA writes to memory: `arm_dcache_delete()` or `cortex_m::cache::invalidate_dcache_by_range()`\n\n### Address Validation Helper (Debug Builds)\n\n**Best practice:** Validate MMIO addresses in debug builds using `is_valid_mmio_address(addr)` checking addr is within valid peripheral ranges (e.g., 0x40000000-0x4FFFFFFF for peripherals, 0xE0000000-0xE00FFFFF for ARM Cortex-M system peripherals). Use `#ifdef DEBUG` guards and halt on invalid addresses.\n\n### Write-1-to-Clear (W1C) Register Pattern\n\nMany status registers (especially i.MX RT, STM32) clear by writing 1, not 0:\n\n```cpp\nuint32_t status = mmio_read(&USB1_USBSTS);\nmmio_write(&USB1_USBSTS, status);  // Write bits back to clear them\n```\n\n**Common W1C:** `USBSTS`, `PORTSC`, CCM status. **Wrong:** `status &= ~bit` does nothing on W1C registers.\n\n### Platform Safety & Gotchas\n\n**⚠️ Voltage Tolerances:**\n\n- Most platforms: GPIO max 3.3V (NOT 5V tolerant except STM32 FT pins)\n- Use level shifters for 5V interfaces\n- Check datasheet current limits (typically 6-25mA)\n\n**Teensy 4.x:** FlexSPI dedicated to Flash/PSRAM only • EEPROM emulated (limit writes <10Hz) • LPSPI max 30MHz • Never change CCM clocks while peripherals active\n\n**STM32 F7/H7:** Clock domain config per peripheral • Fixed DMA stream/channel assignments • GPIO speed affects slew rate/power\n\n**nRF52:** SAADC needs calibration after power-on • GPIOTE limited (8 channels) • Radio shares priority levels\n\n**SAMD:** SERCOM needs careful pin muxing • GCLK routing critical • Limited DMA on M0+ variants\n\n### Modern Rust: Never Use `static mut`\n\n**CORRECT Patterns:**\n\n```rust\nstatic READY: AtomicBool = AtomicBool::new(false);\nstatic STATE: Mutex<RefCell<Option<T>>> = Mutex::new(RefCell::new(None));\n// Access: critical_section::with(|cs| STATE.borrow_ref_mut(cs))\n```\n\n**WRONG:** `static mut` is undefined behavior (data races).\n\n**Atomic Ordering:** `Relaxed` (CPU-only) • `Acquire/Release` (shared state) • `AcqRel` (CAS) • `SeqCst` (rarely needed)\n\n---\n\n## 🎯 Interrupt Priorities & NVIC Configuration\n\n**Platform-Specific Priority Levels:**\n\n- **M0/M0+**: 2-4 priority levels (limited)\n- **M3/M4/M7**: 8-256 priority levels (configurable)\n\n**Key Principles:**\n\n- **Lower number = higher priority** (e.g., priority 0 preempts priority 1)\n- **ISRs at same priority level cannot preempt each other**\n- Priority grouping: preemption priority vs sub-priority (M3/M4/M7)\n- Reserve highest priorities (0-2) for time-critical operations (DMA, timers)\n- Use middle priorities (3-7) for normal peripherals (UART, SPI, I2C)\n- Use lowest priorities (8+) for background tasks\n\n**Configuration:**\n\n- C/C++: `NVIC_SetPriority(IRQn, priority)` or `HAL_NVIC_SetPriority()`\n- Rust: `NVIC::set_priority()` or use PAC-specific functions\n\n---\n\n## 🔒 Critical Sections & Interrupt Masking\n\n**Purpose:** Protect shared data from concurrent access by ISRs and main code.\n\n**C/C++:**\n\n```cpp\n__disable_irq(); /* critical section */ __enable_irq();  // Blocks all\n\n// M3/M4/M7: Mask only lower-priority interrupts\nuint32_t basepri = __get_BASEPRI();\n__set_BASEPRI(priority_threshold << (8 - __NVIC_PRIO_BITS));\n/* critical section */\n__set_BASEPRI(basepri);\n```\n\n**Rust:** `cortex_m::interrupt::free(|cs| { /* use cs token */ })`\n\n**Best Practices:**\n\n- **Keep critical sections SHORT** (microseconds, not milliseconds)\n- Prefer BASEPRI over PRIMASK when possible (allows high-priority ISRs to run)\n- Use atomic operations when feasible instead of disabling interrupts\n- Document critical section rationale in comments\n\n---\n\n## 🐛 Hardfault Debugging Basics\n\n**Common Causes:**\n\n- Unaligned memory access (especially on M0/M0+)\n- Null pointer dereference\n- Stack overflow (SP corrupted or overflows into heap/data)\n- Illegal instruction or executing data as code\n- Writing to read-only memory or invalid peripheral addresses\n\n**Inspection Pattern (M3/M4/M7):**\n\n- Check `HFSR` (HardFault Status Register) for fault type\n- Check `CFSR` (Configurable Fault Status Register) for detailed cause\n- Check `MMFAR` / `BFAR` for faulting address (if valid)\n- Inspect stack frame: `R0-R3, R12, LR, PC, xPSR`\n\n**Platform Limitations:**\n\n- **M0/M0+**: Limited fault information (no CFSR, MMFAR, BFAR)\n- **M3/M4/M7**: Full fault registers available\n\n**Debug Tip:** Use hardfault handler to capture stack frame and print/log registers before reset.\n\n---\n\n## 📊 Cortex-M Architecture Differences\n\n| Feature            | M0/M0+                   | M3       | M4/M4F                | M7/M7F               |\n| ------------------ | ------------------------ | -------- | --------------------- | -------------------- |\n| **Max Clock**      | ~50 MHz                  | ~100 MHz | ~180 MHz              | ~600 MHz             |\n| **ISA**            | Thumb-1 only             | Thumb-2  | Thumb-2 + DSP         | Thumb-2 + DSP        |\n| **MPU**            | M0+ optional             | Optional | Optional              | Optional             |\n| **FPU**            | No                       | No       | M4F: single precision | M7F: single + double |\n| **Cache**          | No                       | No       | No                    | I-cache + D-cache    |\n| **TCM**            | No                       | No       | No                    | ITCM + DTCM          |\n| **DWT**            | No                       | Yes      | Yes                   | Yes                  |\n| **Fault Handling** | Limited (HardFault only) | Full     | Full                  | Full                 |\n\n---\n\n## 🧮 FPU Context Saving\n\n**Lazy Stacking (Default on M4F/M7F):** FPU context (S0-S15, FPSCR) saved only if ISR uses FPU. Reduces latency for non-FPU ISRs but creates variable timing.\n\n**Disable for deterministic latency:** Configure `FPU->FPCCR` (clear LSPEN bit) in hard real-time systems or when ISRs always use FPU.\n\n---\n\n## 🛡️ Stack Overflow Protection\n\n**MPU Guard Pages (Best):** Configure no-access MPU region below stack. Triggers MemManage fault on M3/M4/M7. Limited on M0/M0+.\n\n**Canary Values (Portable):** Magic value (e.g., `0xDEADBEEF`) at stack bottom, check periodically.\n\n**Watchdog:** Indirect detection via timeout, provides recovery. **Best:** MPU guard pages, else canary + watchdog.\n\n---\n\n## 🔄 Workflow\n\n1. **Clarify Requirements** → target platform, peripheral type, protocol details (speed, mode, packet size)\n2. **Design Driver Skeleton** → constants, structs, compile-time config\n3. **Implement Core** → init(), ISR handlers, buffer logic, user-facing API\n4. **Validate** → example usage + notes on timing, latency, throughput\n5. **Optimize** → suggest DMA, interrupt priorities, or RTOS tasks if needed\n6. **Iterate** → refine with improved versions as hardware interaction feedback is provided\n\n---\n\n## 🛠 Example: SPI Driver for External Sensor\n\n**Pattern:** Create non-blocking SPI drivers with transaction-based read/write:\n\n- Configure SPI (clock speed, mode, bit order)\n- Use CS pin control with proper timing\n- Abstract register read/write operations\n- Example: `sensorReadRegister(0x0F)` for WHO_AM_I\n- For high throughput (>500 kHz), use DMA transfers\n\n**Platform-specific APIs:**\n\n- **Teensy 4.x**: `SPI.beginTransaction(SPISettings(speed, order, mode))` → `SPI.transfer(data)` → `SPI.endTransaction()`\n- **STM32**: `HAL_SPI_Transmit()` / `HAL_SPI_Receive()` or LL drivers\n- **nRF52**: `nrfx_spi_xfer()` or `nrf_drv_spi_transfer()`\n- **SAMD**: Configure SERCOM in SPI master mode with `SERCOM_SPI_MODE_MASTER`\n\n## Limitations\n- Use this skill only when the task clearly matches the scope described above.\n- Do not treat the output as a substitute for environment-specific validation, testing, or expert review.\n- Stop and ask for clarification if required inputs, permissions, safety boundaries, or success criteria are missing.","tags":["arm","cortex","expert","antigravity","awesome","skills","sickn33","agent-skills","agentic-skills","ai-agent-skills","ai-agents","ai-coding"],"capabilities":["skill","source-sickn33","skill-arm-cortex-expert","topic-agent-skills","topic-agentic-skills","topic-ai-agent-skills","topic-ai-agents","topic-ai-coding","topic-ai-workflows","topic-antigravity","topic-antigravity-skills","topic-claude-code","topic-claude-code-skills","topic-codex-cli","topic-codex-skills"],"categories":["antigravity-awesome-skills"],"synonyms":[],"warnings":[],"endpointUrl":"https://skills.sh/sickn33/antigravity-awesome-skills/arm-cortex-expert","protocol":"skill","transport":"skills-sh","auth":{"type":"none","details":{"cli":"npx skills add sickn33/antigravity-awesome-skills","source_repo":"https://github.com/sickn33/antigravity-awesome-skills","install_from":"skills.sh"}},"qualityScore":"0.700","qualityRationale":"deterministic score 0.70 from registry signals: · indexed on github topic:agent-skills · 34964 github stars · SKILL.md body (12,815 chars)","verified":false,"liveness":"unknown","lastLivenessCheck":null,"agentReviews":{"count":0,"score_avg":null,"cost_usd_avg":null,"success_rate":null,"latency_p50_ms":null,"narrative_summary":null,"summary_updated_at":null},"enrichmentModel":"deterministic:skill-github:v1","enrichmentVersion":1,"enrichedAt":"2026-04-25T00:50:28.454Z","embedding":null,"createdAt":"2026-04-18T21:31:28.040Z","updatedAt":"2026-04-25T00:50:28.454Z","lastSeenAt":"2026-04-25T00:50:28.454Z","tsv":"'+17':326 '-1':777,1313 '-2':1042,1316,1318,1321 '-25':860 '-256':1004 '-4':998 '-7':1054 '/m4':231 '/m7':213 '/rust':327 '0':667,796,1016,1041 '0x0f':1575 '0x40000000':753 '0x40000000-0x4fffffff':752 '0x4fffffff':754 '0xdeadbeef':1449 '0xe0000000':758 '0xe0000000-0xe00fffff':757 '0xe00fffff':759 '1':634,794,1019,1470 '100':1305 '10hz':874 '180':1307 '2':669,997,1483 '3':686,1053,1493 '3.3':839 '30mhz':877 '32':604,618,648,661 '4':193,408,581,863,1505,1593 '5':1514 '50':1303 '500':1583 '512':653,666,668 '5v':842,852 '6':859,1525 '600':200,1309 '8':911,1003,1064,1130 'abstract':126,275,336,1569 'access':491,544,641,956,1098,1192,1430 'acqrel':982 'acquire/release':979 'action':93 'activ':884 'adc':263 'add':458 'addr':743,745 'address':725,734,742,775,1223,1249 'adjac':623 'advanc':291 'affect':898 'align':310,598,606,621,647,660 'allow':1163 'alway':1417 'annot':367 'api':256,1504,1591 'appli':85 'architectur':140,1294 'arduino':289 'arduino/bare-metal':232 'arm':2,16,26,36,50,65,114,313,403,416,425,575,607,697,714,761 'arm-cortex-expert':1,25,35,49,64 'around':525 'ask':1667 'asm':518,523 'assign':895 'async':390 'atom':973,1171 'atomicbool':942,943 'attribut':643,646 'audio':265 'avail':1276 'avoid':305 'back':812 'background':1066 'balanc':312 'bare':130,300 'bare-met':129,299 'barrier':174,318,385,413,449,496,502,555 'base':189,1553 'basepri':1123,1125,1127,1137,1138,1158 'basic':1187 'before/after':497 'behavior':970 'best':44,87,631,730,1148,1426,1462 'bfar':1246,1271 'bit':811,824,1133,1407,1560 'ble':223,270 'block':255,380,388,1112,1547 'bottom':1452 'boundari':1675 'buffer':155,370,378,603,614,652,664,1499 'build':729,737 'byte':605,619 'c':242,325,642,659 'c/c':488,1069,1104 'c/spi/uart/adc/dac/pwm/usb':123 'c/usb/ble':343 'cach':169,205,308,568,572,587,596,611,626,687,704,720,1338,1344,1347 'cacheabl':638,675,683 'calibr':904 'call':381 'canari':1443,1467 'cannot':1025 'captur':1283 'care':920 'cas':983 'caus':1189,1243 'ccm':820,880 'cdc/msc/hid':272 'cfsr':1236,1269 'chang':485,879 'channel':912 'check':744,854,1227,1235,1244,1453 'checklist':47 'clarif':1669 'clarifi':79,1471 'clean':125,705 'clear':780,791,814,1405,1642 'clock':881,887,1302,1557 'code':179,1103,1213 'codebas':279 'coher':323,573 'comment':180,1184 'common':816,1188 'compet':234 'compil':108,1490 'compile-tim':1489 'complet':107,356,560 'concurr':151,1097 'condit':307 'config':889,1492 'configur':672,677,990,1007,1068,1237,1402,1427,1555,1623 'constant':1487 'constexpr':332 'constraint':81,172 'context':1368,1376 'control':1565 'cooper':158,293 'core':233,1495 'correct':349,937 'corrupt':622,1202 'cortex':3,18,27,37,51,66,116,198,211,221,229,315,405,418,427,516,521,577,609,702,718,763,1140,1292 'cortex-m':17,115,762,1291 'cortex-m0':228 'cortex-m4':210,220 'cortex-m7':197,314,404,417,426,576,608 'cost':335 'coupl':203 'cpp':797,1105 'cpu':396,435,590,640,977 'cpu-on':976 'creat':505,528,1395,1544 'criteria':1678 'critic':400,424,574,600,925,957,1046,1088,1108,1134,1151,1180 'cross':338 'cross-mcu':337 'cs':960,964,1144,1146,1563 'current':856 'd':1346 'd-cach':1345 'data':250,494,500,586,594,971,1095,1211,1601 'datasheet':855 'dcach':698,706,715,722 'debug':452,728,736,769,1186,1277 'dedic':866 'default':375,1372 'delay':460 'delet':700,716 'deliv':106 'derefer':1198 'describ':1646 'design':187,1484 'despit':475 'detail':98,1242,1478 'detect':1457 'determin':166 'determinist':1400 'develop':14 'devic':579 'differ':71,593,1295 'disabl':1106,1177,1398 'disappear':481 'dma':167,206,257,570,588,602,693,710,893,927,1048,1517,1586 'dma/cache':322 'dmb':493,519 'document':386,1179 'domain':72,888 'doubl':1337 'driven':249 'driver':13,111,121,186,215,239,357,1485,1539,1549,1612 'drv':1619 'dsb':499,524 'dsp':1319,1322 'dtcm':657,1353 'dtcm.bss':645 'dtcm/sram':635 'dwt':1354 'e.g':751,1014,1448 'eeprom':870 'effect':170,466 'effici':324 'els':1466 'embed':6,330 'emul':871 'enabl':1110 'engin':8 'environ':1658 'environment-specif':1657 'especi':787,1193 'event':156 'exampl':99,361,1507,1537,1573 'except':844 'execut':470,1210 'expert':4,28,38,52,67,1663 'explain':365 'extern':1541 'f4/f7/h7':208 'f7/h7':411,584,886 'face':1503 'fail':454 'failur':479 'fals':945 'fastest':639 'fault':1233,1238,1248,1266,1274,1359,1437 'feasibl':1174 'featur':1296 'feedback':1534 'firmwar':11,109 'first':350 'fix':892 'flash':393 'flash/psram':868 'flexspi':865 'flow':373 'flush':699 'focus':175 'fpccr':1404 'fpscr':1380 'fpu':1329,1367,1375,1386,1392,1403,1419 'frame':1254,1285 'free':1143 'freerto':297 'freertos/zephyr':160 'ft':846 'full':354,1273,1364,1365,1366 'function':507,1087 'gclk':923 'get':1124 'goal':80 'gotcha':832 'gpio':837,896 'gpiot':909 'group':1030 'guard':376,770,1424,1464 'guidanc':43,141 'hal':128,143,286,542,1075,1604,1607 'hal/ll':214 'halt':772 'handl':1360 'handler':1281,1498 'hard':1409 'hardfault':1185,1229,1280,1362 'hardwar':437,476,1532 'heap/data':1206 'helper':506,727 'hfsr':1228 'high':261,1165,1581 'high-prior':1164 'high-throughput':260 'higher':1012 'highest':1039 'i-cach':1342 'i.mx':195,788 'i2c':1060 'ifdef':768 'illeg':1207 'implement':119,267,486,1494 'implicit':459 'improv':1529 'indirect':1456 'inform':1267 'init':359,1496 'input':84,1672 'inspect':1224,1252 'instead':1175 'instruct':78,469,563,1208 'integr':161,283 'interact':1533 'interfac':853 'intermitt':478 'intern':366 'interrupt':145,248,987,1090,1120,1142,1178,1518 'interrupt-driven':247 'invalid':627,721,774,1221 'invers':383 'irq':1107,1111 'irqn':1072 'isa':1311 'isr':153,360,372,1020,1100,1167,1384,1393,1416,1497 'itcm':1352 'iter':1526 'keep':1150 'key':1008 'khz':1584 'knowledg':188 'last':689 'latenc':1388,1401,1512 'layer':142,276 'lazi':1370 'level':238,484,849,916,995,1000,1006,1024 'librari':137 'like':530 'limit':857,872,910,926,1001,1263,1265,1361,1440,1634 'line':309,612 'link':655 'll':1611 'load':397 'logic':1500 'lower':1010,1118 'lower-prior':1117 'lowest':1062 'lpspi':875 'lr':1259 'lspen':1406 'm':19,117,517,522,703,719,764,1141,1293 'm0':230,929,1324 'm0/m0':996,1195,1264,1297,1442 'm3':1298 'm3/m4/m7':1002,1037,1114,1226,1272,1439 'm4':212,222 'm4/m4f':1299 'm4f':1332 'm4f/m7f':1374 'm7':199,316,406,419,428,548,578,610 'm7/m7f':1300 'm7f':1335 'ma':861 'macro':529 'magic':1446 'main':1102 'maintain':178 'mainten':597,688 'manag':148 'mani':784 'mask':1091,1115 'master':1627,1633 'match':1643 'matter':547 'max':838,876,1301 'may':558 'mcu':339 'memmanag':1436 'memori':147,173,204,303,317,412,423,433,495,550,624,628,696,713,1191,1219 'messag':340 'metal':131,301 'mhz':201,1304,1306,1308,1310 'microchip/atmel':227 'microcontrol':20 'microsecond':1154 'middl':1051 'midi':273 'millisecond':1156 'miss':384,448,1680 'mmfar':1245,1270 'mmio':320,415,508,510,512,733,741,801,805 'mode':1480,1559,1599,1628,1632 'modern':931 'modifi':513,538 'modul':112,184 'modular':185,278 'mpu':671,685,1323,1423,1431,1463 'mpu-configur':670 'multipl':616 'mut':663,936,963,967 'mutex':948,951 'mux':922 'need':42,69,903,919,986,1524 'never':878,933 'new':944,952,954 'next':468,562 'no-access':1428 'non':254,637,674,682,1391,1546 'non-block':253,1545 'non-cach':636,673,681 'non-fpu':1390 'none':955 'nordic':218 'normal':1056 'note':1509 'noth':826 'nrf':224,287,1618 'nrf52':23,217,901,1613 'nrfx':1614 'null':1196 'number':1011 'nvic':989,1070,1076,1079,1131 'object':105 'ocram/sram':678 'open':102 'oper':344,445,551,1047,1172,1572 'optim':162,351,483,1515 'option':950,1325,1326,1327,1328 'order':422,432,974,1561,1598 'outcom':91 'output':1652 'outsid':75 'overflow':1200,1204,1421 'overrun':379 'pac':1085 'pac-specif':1084 'packet':1481 'page':1425,1465 'pattern':144,152,328,401,487,783,938,1225,1543 'pc':1260 'per':890 'perform':164,348,553 'period':1454 'peripher':120,274,749,756,766,883,891,1057,1222,1475 'permiss':1673 'pin':847,921,1564 'pipelin':251 'placement':629 'platform':118,135,191,281,830,836,992,1262,1474,1589 'platform-specif':134,280,991,1588 'pointer':1197 'portabl':1445 'portsc':819 'possibl':1162 'power':907 'power-on':906 'practic':45,88,731,1149 'precis':1334 'preempt':1017,1026 'preemption':1031 'preemptiv':295 'prefer':1157 'primask':1160 'principl':345,1009 'print':453,457 'print/log':1287 'prio':1132 'prioriti':382,915,988,994,999,1005,1013,1015,1018,1023,1029,1032,1036,1040,1052,1063,1073,1081,1119,1128,1166,1519 'profil':353 'proper':1567 'protect':1093,1422 'protocol':268,1477 'provid':92,138,1460,1536 'purpos':1092 'queue':157 'r0':1256 'r0-r3':1255 'r12':1258 'r3':1257 'race':306,972 'radio':913 'ram':391 'rang':708,724,750 'rare':985 'rate/power':900 'rational':1182 'read':471,498,509,532,565,694,802,1217 'read-on':1216 'read/write':1554,1571 'readi':941 'reads/writes':441,527 'real':1411 'real-tim':1410 'receiv':1609 'recoveri':1461 'reduc':1387 'ref':962 'refcel':949,953 'refin':1527 'reg':533,536,539 'region':676,679,1432 'regist':132,237,368,440,461,473,490,543,556,782,786,829,1231,1240,1275,1288,1570 'register-level':236 'relat':442 'relax':975 'relev':86 'reorder':439,549 'repr':658 'requir':83,101,599,1472,1671 'reserv':1038 'reset':1290 'resort':690 'resources/implementation-playbook.md':103 'return':566 'review':1664 'ring':154 'robust':150 'role':104 'rout':924 'rt':789 'rt1062':196 'rtos':1521 'run':1169 'rust':514,654,932,939,1078,1139 's0':1378 's0-s15':1377 's15':1379 'saadc':902 'safe':374,531,534,537 'safeti':146,304,346,399,831,1674 'safety-crit':398 'samd':24,226,290,917,1622 'save':1369,1381 'schedul':159,296,302 'scope':77,1645 'sdio':246 'sdk':288 'sdk/zephyr':225 'section':644,656,958,1089,1109,1135,1152,1181 'see':592 'semiconductor':219 'senior':5 'sensor':1542 'sensorreadregist':1574 'seqcst':984 'sercom':918,1624,1630 'seri':209 'set':1080,1126,1136 'setprior':1071,1077 'share':914,980,1094 'shifter':850 'short':1153 'show':149 'singl':1333,1336 'size':613,615,1482 'skeleton':1486 'skill':31,57,1637 'skill-arm-cortex-expert' 'slew':899 'slowest':691 'snippet':364 'softwar':7,139,177 'solut':355 'source-sickn33' 'sp':1201 'special':9 'specif':136,282,993,1086,1590,1659 'speed':897,1479,1558,1597 'spi':243,264,1059,1538,1548,1556,1605,1608,1615,1620,1626,1631 'spi.begintransaction':1595 'spi.endtransaction':1602 'spi.transfer':1600 'spi/i':342 'spiset':1596 'stack':269,1199,1253,1284,1371,1420,1434,1451 'stack/heap':311 'stale':472,567 'state':947,981 'state.borrow':961 'static':649,662,935,940,946,966 'status':785,800,809,821,823,1230,1239 'step':94 'stm32':22,207,285,410,583,790,845,885,1603 'stm32cubemx':216 'stop':1665 'strategi':630 'stream/channel':894 'struct':1488 'structur':371 'sub':1035 'sub-prior':1034 'substitut':1655 'success':1677 'suggest':1516 'symptom':446 'synchron':501 'system':765,1413 'take':465 'target':190,1473 'task':39,60,1067,1522,1641 'tcm':1348 'teensi':21,192,407,580,862,1592 'teensyduino':284 'templat':331 'test':1661 'testabl':183 'threshold':1129 'throughput':262,394,1513,1582 'thumb':1312,1315,1317,1320 'tight':202 'time':171,1045,1397,1412,1491,1511,1568 'time-crit':1044 'timeout':1459 'timer':1049 'tip':1278 'to-clear':778 'token':1147 'toler':834,843 'tool':74 'topic':292 'topic-agent-skills' 'topic-agentic-skills' 'topic-ai-agent-skills' 'topic-ai-agents' 'topic-ai-coding' 'topic-ai-workflows' 'topic-antigravity' 'topic-antigravity-skills' 'topic-claude-code' 'topic-claude-code-skills' 'topic-codex-cli' 'topic-codex-skills' 'tradeoff':387 'transact':1552 'transaction-bas':1551 'transfer':168,1587,1621 'transmit':1606 'treat':1650 'trigger':1435 'type':1234,1476 'typic':858 'u8':665 'uart':244,266,1058 'uint32':798,1121 'uint8':650 'unalign':1190 'undefin':969 'unit':182 'unit-test':181 'unrel':62 'updat':477 'usag':258,362,369,1508 'usb':271 'usb1':803,807 'usbst':804,808,818 'use':29,55,127,515,738,767,848,934,1050,1061,1083,1145,1170,1279,1385,1418,1562,1585,1635 'user':1502 'user-fac':1501 'v':840 'valid':90,726,732,740,748,1251,1506,1660 'valu':474,569,1444,1447 'variabl':1396 'variant':930 'verif':96 'version':1530 'via':684,1458 'violat':620 'volatil':526 'voltag':833 'vs':294,389,392,395,1033 'w1c':781,817,828 'watchdog':1455,1468 'weak':421,431 'weakly-ord':420,430 'within':747 'without':455,554,595 'work':33,450 'workflow':41,1469 'worst':633 'wrap':489,541 'write':235,462,504,511,535,557,711,776,793,806,810,873,1214 'wrong':822,965 'x':194,409,582,864,1594 'xfer':1616 'xpsr':1261 'yes':1356,1357,1358 'zephyr':298 'zero':334 'zero-cost':333","prices":[{"id":"36223608-79d7-4d78-830a-f4cc103c5b02","listingId":"a48ba7ec-15a2-484f-8c56-975568f7313f","amountUsd":"0","unit":"free","nativeCurrency":null,"nativeAmount":null,"chain":null,"payTo":null,"paymentMethod":"skill-free","isPrimary":true,"details":{"org":"sickn33","category":"antigravity-awesome-skills","install_from":"skills.sh"},"createdAt":"2026-04-18T21:31:28.040Z"}],"sources":[{"listingId":"a48ba7ec-15a2-484f-8c56-975568f7313f","source":"github","sourceId":"sickn33/antigravity-awesome-skills/arm-cortex-expert","sourceUrl":"https://github.com/sickn33/antigravity-awesome-skills/tree/main/skills/arm-cortex-expert","isPrimary":false,"firstSeenAt":"2026-04-18T21:31:28.040Z","lastSeenAt":"2026-04-25T00:50:28.454Z"}],"details":{"listingId":"a48ba7ec-15a2-484f-8c56-975568f7313f","quickStartSnippet":null,"exampleRequest":null,"exampleResponse":null,"schema":null,"openapiUrl":null,"agentsTxtUrl":null,"citations":[],"useCases":[],"bestFor":[],"notFor":[],"kindDetails":{"org":"sickn33","slug":"arm-cortex-expert","github":{"repo":"sickn33/antigravity-awesome-skills","stars":34964,"topics":["agent-skills","agentic-skills","ai-agent-skills","ai-agents","ai-coding","ai-workflows","antigravity","antigravity-skills","claude-code","claude-code-skills","codex-cli","codex-skills","cursor","cursor-skills","developer-tools","gemini-cli","gemini-skills","kiro","mcp","skill-library"],"license":"mit","html_url":"https://github.com/sickn33/antigravity-awesome-skills","pushed_at":"2026-04-24T06:41:17Z","description":"Installable GitHub library of 1,400+ agentic skills for Claude Code, Cursor, Codex CLI, Gemini CLI, Antigravity, and more. Includes installer CLI, bundles, workflows, and official/community skill collections.","skill_md_sha":"355f25b1a39a66dc48f42df9188265e502401f5b","skill_md_path":"skills/arm-cortex-expert/SKILL.md","default_branch":"main","skill_tree_url":"https://github.com/sickn33/antigravity-awesome-skills/tree/main/skills/arm-cortex-expert"},"layout":"multi","source":"github","category":"antigravity-awesome-skills","frontmatter":{"name":"arm-cortex-expert","description":"Senior embedded software engineer specializing in firmware and driver development for ARM Cortex-M microcontrollers (Teensy, STM32, nRF52, SAMD)."},"skills_sh_url":"https://skills.sh/sickn33/antigravity-awesome-skills/arm-cortex-expert"},"updatedAt":"2026-04-25T00:50:28.454Z"}}